This invention relates generally to programmable logic devices. More particularly, this invention relates to a programmable logic device with a unified cell structure including signal interface bumps to facilitate improved signal integrity.
Increasing die sizes and packaging densities of programmable logic devices has resulted in both longer and finer signal paths. These paths have resulted in increased signal skew, signal delay, and diminished signal integrity. It would be highly desirable to reduce these problems associated with prior art programmable logic devices.
Prior art programmable logic devices typically have their signal input/output connections in a peripheral configuration. It would be highly desirable to provide a programmable logic device with standard cell elements resulting in a simplified input/output connection architecture. Such a feature would simplify the layout, routing, and fabrication of the programmable logic device. Such a feature would also improve signal integrity associated with the programmable logic device.
A programmable logic device includes a set of aligned unified cells, with each unified cell including a set of signal interface bumps. An input/output band of each unified cell is aligned with input/output bands of adjacent unified cells. A trace is positioned between each signal interface bump of a unified cell and the input/output band of the unified cell. The input/output band of each unified cell is responsible for providing an input/output interface for the logic array block(s) of that unified cell.
In another aspect of the invention, a grid of signal interface bumps is formed on a die. A package with a solder ball is positioned within the grid of signal interface bumps. A set of package routing leads connects the grid of signal interface bumps and the solder ball. External signals can be provided to the unified cells via the solder ball and the package routing leads.
The invention provides a programmable logic device with standard cell elements resulting in a regular signal input/output connection architecture. This simplifies the layout, routing, and fabrication of the programmable logic device. The chip-to-package connections of the invention improve signal integrity associated with the programmable logic device.